Direct Memory Access has been the foundation of CPU-device communication for decades. The CPU sets up a descriptor ring — a circular buffer of commands describing where data should go. The DMA engine reads the descriptors, moves data between device and memory without CPU involvement, and signals completion via an interrupt. This frees the CPU from the tedium of data transfer. Every operating systems textbook teaches it. Every high-performance I/O system relies on it.
On modern cache-coherent interconnects, programmed I/O — the method DMA was invented to replace — is faster.
The observation: CXL 3.0 and similar coherent interconnects give devices a view of the CPU's cache hierarchy. A CPU store to a device-mapped address propagates through the same coherence protocol that maintains consistency between CPU cores. The latency of this path — a cache-line write — is fundamentally smaller than the latency of setting up a DMA descriptor, triggering an engine, and handling an interrupt.
For fine-grained communication (small messages, low-latency requirements), the DMA stack adds overhead that exceeds the data transfer itself. The descriptor ring, the doorbell, the interrupt handler, the context switch — each step serves a purpose in a world where CPU-device communication is expensive and should be batched. In a world where that communication is a cache-line operation, the batching infrastructure costs more than it saves.
The structural point: DMA was never solving a fundamental problem. It was compensating for the incoherence of the bus. The bus didn't understand memory consistency, so a specialized engine was needed to move data across the boundary. Once the interconnect is coherent — once the device participates in the same consistency protocol as the CPUs — the simplest possible data movement (load/store) becomes the best.
Forty years of systems complexity — descriptor formats, ring buffer management, interrupt coalescing, DMA scatter-gather lists — were compensation for a hardware limitation. The limitation is gone. The complexity remains, embedded in every driver, every OS, every systems programming curriculum. The bypass that was built to work around a bottleneck has become the bottleneck.